1. Field of Invention
The present invention relates to a method for operating a non-volatile memory (NVM). More particularly, the present invention relates to a method for operating an n-channel non-volatile memory.
2. Description of Related Art
A stacked gate memory has the property of permanently storing information that can be repeatedly read, written or erased. Moreover, the stacked gate memory also has the advantage of retaining information even when power is interrupted. Stacked gate memory is thus a type of non-volatile memory device that is widely used in personal computer and electronic systems.
A typical stacked gate memory comprises a doped polysilicon floating gate and a doped polysilicon control gate. The programming and the erasing of this type of stacked gate memory is accomplished by applying appropriate voltages to the source/drain regions and to the control gate; thereby causing electrons to inject into and to eject from the polysilicon floating gate.
In general, the common modes for the stacked gate memory to inject electron include the channel hot-electron injection and the Fowler-Nordheim tunneling. The programming or the erasing of the device depends on an injection or an ejection of electrons.
Additionally, a stacked gate memory device can further divide into a p-channel stacked gate memory device and an n-channel stacked gate memory device. Since the n-channel stacked gate memory device has a higher carrier mobility, a higher reading current and a faster reading speed are provided. Moreover, the programming of the n-channel stacked gate memory device is normally accomplished by the channel hot-electron injection while the erasing is accomplished by ejecting electrons to the source side by the Fowler-Nordheim tunneling effect.
Referring to FIG. 1, FIG. 1 is simplified circuit diagram for a conventional n-channel stacked gate memory device array. A plurality of memory cells Qm1 to Qm4, a plurality of bit lines BL1, BL2 and a plurality of word lines WL1, WL2 are shown in FIG. 1. The drain regions of the memory cells Qm1 and Qm3 are coupled to the bit line BL1 and the drain regions of memory cells Qm2 and Qm4 are coupled to bit line BL2. The control gates of the memory cells Qm1 and Qm2 are coupled to the word line WL1, and the control gates of the memory cells Qm3 and Qm4 are coupled to the word line WL2. The source regions of the memory cells Qm1 to Qm4 share a common source line (SL).
Referring to Table 1 and FIGS. 2A to 2B, FIGS. 2A to 2B demonstrate the programming (FIG. 2A), the reading and the erasing operations (FIG. 2B) of an n-channel stacked gate memory device. Table 1 summarizes the appropriate voltages that are applied for the various operations of the memory cell Qm1.
As shown in Table 1, FIGS. 2A and 2B, 9 to 12 volts of bias Vcg is applied to the word line WL1 (control gate 208) and 5 to 7 volts of bias Vd is applied to the bit line BL1 (drain region 202) during the programming of the memory cell Qm1. The source line SL (source region 204) and the P-well (or substrate) 200 are at 0 volt. Under such a bias condition, a large channel current (0.25xcx9c1 mamp/memory cell) is generated, and electrons then travel from the end of the source region 204 to the end of the drain region 202. Hot electrons, which have sufficient momentum to overcome the energy barrier of the tunnel oxide layer, are generated when the electrons are accelerated by the high channel electric field at the end of the drain region 202 to generate hot electrons. Additionally, a high positive bias is applied to the control gate 208 causing the hot electrons to inject into the floating gate 206 from the drain region 202 as shown in FIG. 2A. After the programming operation, the threshold voltage (VT) of the memory cell increases due to the residual negative charges in the floating gate 206. These charges would remain in the floating gate 206 for a long period of time (for example, approximately for ten years at room temperature), unless they are removed intentionally.
As information is being read from the memory cell Qm1, a bias of Vd volt is applied to the bit line BL1 (drain region 202), a bias Vcc is applied to the word line WL1 (control gate 206), a bias of 0 volt is applied to the source line SL (source region 204) and a bias of 0 volt is applied to the P-well. Since the channel of such a memory cell is closed and the current is low when electrons are present in the floating gate 206, and the channel of the memory cell is opened and the current is high when electrons are absent in the floating gate, the logic xe2x80x9c1xe2x80x9d or the logic xe2x80x9c0xe2x80x9d stored in the memory cell is determined by the opening/closing of the channel and the size of the current flow.
To erase the memory cell Qm1, it is conventionally accomplished by the Fowler-Nordheim tunneling effect from the source side. A negative bias xe2x88x92Vcg of about xe2x88x928 volts to about xe2x88x9212 volts is applied to the word line WL1 (control gate 208), a bias Vs of about 4xcx9c6 volts is applied to the source line SL (source region 204). Moreover, the bit line BL1 (drain region 202) is floating while a bias of 0 volt is applied to the P-well 200. Consequently, a great electric field is formed between the floating gate and a portion of the source region that is overlapped with the floating gate. Electrons are thus tunneled to the source region 204 from the floating gate 206 by the Fowler-Nordheim effect as shown in FIG. 2B.
The programming of the above stacked gate memory device is based on the channel hot electron, wherein electrons are injected from the drain side. The effectiveness of electron injection is thereby very low. A higher voltage is thus required to provide a higher current during programming to improve the programming speed. A higher voltage, however, reduces the reliability of electronic devices and limits the size reduction of the device.
Moreover, based on the bias setups (WL1 as xe2x88x92Vcg, SL as +Vs) shown in FIG. 1 and table 1, when Qm1 is erased, the memory cell Qm2 is also erased. Therefore, when a stacked gate memory device is erased according to the prior art, a sector of memory cells is erased rather than a single memory cell. Many limitations are imposed on the programming and erasing of such a device. In other words, the conventional stacked gate memory device must perform the erasing and the coding actions to complete the writing of new information. Therefore, writing of new information requires a writing of all information every time (because it needs to erase the existing information first before any coding can be done). The operational speed for the writing operation of a stacked gate memory device is thus limited.
The present invention provides a method for operating a nonvolatile memory device, where the memory device can program or erase cell-by-cell, by byte, by sector and by block.
The present invention provides a method for operating a non-volatile memory device, wherein the current flow of the memory device is lowered to increase the operating speed of the memory device.
The present invention provides a method for operating a non-volatile memory device, wherein to program the memory cell by the channel FN tunneling effect, a positive voltage is applied to the control gate, a negative voltage is applied to the drain region, the source region is floating and a negative voltage is applied to the substrate. Moreover, a negative voltage is applied to the control gate, a positive voltage is applied to the drain region, the source region is floating and a positive voltage is applied to the substrate to erase the memory cell by the channel FN tunneling effect.
According to the present invention, the channel FN tunnel effect is used for the coding and the erasing of the non-volatile memory device. A deep doped drain is also obviated from forming at the vicinity of the overlapped region between the floating gate and the source/drain region. The distance between the source region and the drain of the present invention can thus decrease without the short channel effect. In other words, the floating gate length can be reduced to increase the integration of the device without intensifying the short channel effect. Additionally, the FN tunneling effect is used for the coding operation, the effectiveness of electron injection is higher, and the current flow (about 10 nA/cell) of the memory cell during the coding operation is lower to reduce the power consumption and improve the operation speed. To program and to erase a flash cell using the FN tunneling effect, the cell current is small during operations. It implies that the power consumption of the whole chip can be significantly reduced by this invention.
The method for operating the nonvolatile memory device of the present invention, which is applicable on a memory cell array that includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines, wherein the memory cells are arranged in rows and columns. The drain region of each memory cell in every row is coupled with a corresponding bit line. The source region of each memory cell in every row is coupled with a corresponding source line. The control gate of each memory cell in each row is coupled with a corresponding word line. The method for operating the nonvolatile memory device according an embodiment of the present invention comprises applying a first positive voltage to the word line that is coupled to a selected memory cell, a first negative voltage is applied to the bit line that is coupled to the selected memory cell, and a second negative voltage is applied to the substrate of the memory cell array. The source line that is coupled to the selected memory cell is floating and the bit lines that are coupled to all other memory cells that share a common word line with that selected memory cell are grounded. The non-selected memory cells that share a common word line with the selected memory cell are thus prevented from being programmed. When the nonvolatile memory device is erased, a third negative voltage is applied to the word line that is coupled to the selected memory cell and a second positive voltage is applied to the bit line that is coupled to the selected memory cell. A third positive voltage is also applied to the substrate of the memory cell array, and the source line that is coupled to the selected memory cell is floating, while the bit lines that are coupled to the other non-selected memory cells which share a common word line with the selected memory cell are grounded. The non-selected memory cells that share a common word line with the selected memory cell are thus prevented from being erased.
In another aspect of the present invention, the memory cells that are connected by the same bit line may also have a common well line. During the programming of the selected cell, the second negative voltage is applied to the well line that is coupled to the selected memory cell, while the well lines that are coupled to all other memory cells that share a common word line with the selected memory cell are set floating. During the erasing of the selected cell, the third positive voltage is applied to the well line that is coupled to the selected cell, while the well lines that are coupled to all other memory cells that share a common word line with the selected memory cell are floating.
The nonvolatile memory device of the present invention is programmed or erased cell-by-cell in an array of memory cells. Unlike the conventional electrically erasable and programmable read only memory (EEPROM), two transistors are required to accomplish the cell-by-cell programming and erasing. The space between the device is thereby reduced and the integration of the device is correspondingly increased. Moreover, the complexity of the process is decreased.
Additionally, the nonvolatile memory device according to the present invention can also program and erase by byte, by sector or by block simply by controlling the bias at the various word lines and bit lines.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.